Method of manufacturing a semiconductor device and a semiconductor device

ABSTRACT

In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.17/722,867 filed Apr. 18, 2022, which is a continuation of U.S. patentapplication Ser. No. 16/370,668 filed on Mar. 29, 2019, now U.S. Pat.No. 11,309,417, which is a divisional of U.S. patent application Ser.No. 15/966,761 filed on Apr. 30, 2018, now U.S. Pat. No. 10,276,719, theentire content of each of which is incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a semiconductor integrated circuit, and moreparticularly to a semiconductor device having fin field effecttransistors and their manufacturing process.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower costs, challenges from both fabrication and design issues haveresulted in the development of three-dimensional designs, such as amulti-gate field effect transistor (FET), including a fin FET (FinFET)and a gate-all-around (GAA) FET. In a FinFET, a gate electrode layer isadjacent to three side surfaces of a channel region with a gatedielectric layer interposed therebetween. Because the gate structuresurrounds (wraps) the fin on three surfaces, the transistor essentiallyhas three gates controlling the current through the fin or channelregion. The current driving capacity of the FinFET is generallydetermined by a number of the fins, a fin width and a fin height at thechannel region.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIGS. 1A and 1B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 2A and 2B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 3A and 3B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 4A and 4B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 5A and 5B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 6A and 6B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 7A and 7B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 8A and 8B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 9A and 9B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 10A and 10B one of the various stages of sequential processes formanufacturing a semiconductor device according to an embodiment of thepresent disclosure.

FIGS. 11A and 11B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 12A and 12B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 13A and 13B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 14A, 14B, 14C and 14D show one of the various stages of sequentialprocesses for manufacturing a semiconductor device according to anembodiment of the present disclosure.

FIGS. 15A and 15B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 16A and 16B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 17A and 17B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to an embodiment ofthe present disclosure.

FIGS. 18A and 18B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 19A and 19B show stages of sequential processes for manufacturinga semiconductor device according to another embodiment of the presentdisclosure.

FIGS. 20A, 2B, 20C and 20D show semiconductor devices according to otherembodiments of the present disclosure.

FIGS. 21A and 21B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 22A and 22B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 23A and 23B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 24A and 24B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 25A and 25B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 26A and 26B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 27A and 27B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 28A and 28B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 29A and 29B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 30A and 30B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 31A and 31B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 32A and 32B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 33A and 33B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 34A and 34B show one of the various stages of sequential processesfor manufacturing a semiconductor device according to another embodimentof the present disclosure.

FIGS. 35A, 35B, 35C and 35D show simulation conditions.

FIGS. 36A and 36B show simulated results.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific embodiments or examples of components andarrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, dimensions of elements are not limited to thedisclosed range or values, but may depend upon process conditions and/ordesired properties of the device. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“made of” may mean either “comprising” or “consisting of.” In thisdisclosure, the phrase “at least one of A, B and C means “A, B and/or C”(A, B, C, A+B, A+C, B+C A+B+C), and does not mean one from A, one from Band one from C, unless otherwise described.

With the decrease of dimensions of semiconductor devices, for example,FinFETs and GAA FETs, structures and/or configurations of source/drainregions need to be improved to decrease contact resistance between aconductive contact (metallic layer) and the source/drain regions(semiconductor), and to provide appropriate stress to a channel regionby the source/drain regions. To apply the stress to the source/drainregions of FinFETs or GAA FETs, one or more epitaxial semiconductorlayers are formed. To decrease the contact resistance, a wrap-aroundcontact that covers the top and side faces of the fin source/drainregions is employed.

However, the source/drain epitaxial layer tends to have a diamond crosssectional shape connecting adjacent fin source/drain structures. Inparticular, a void is often formed between the fin structures, whichcauses various issues. In the wrap-around contact structure, noepitaxial semiconductor layer is generally formed, and thus thestructure does not provide stress to the channel region. Further, eventhough the contact resistance can be reduced with the wrap-aroundstructure, fin volume is reduced and thus fin resistance may increase.

In the present disclosure, source/drain epitaxial structures having aflat top surface for FinFETs and GAA FETs and fabrication method thereofare provided.

In the following embodiments, material, configurations, dimensionsand/or processes of one embodiment may be employed in anotherembodiment, unless otherwise described, and detailed explanation thereofmay be omitted. In the following embodiments, a semiconductor (e.g., Si,Ge, SiGe, etc), a semiconductor layer, and an epitaxial layer generallyand the like refer to single crystalline, unless otherwise explained.

FIGS. 1-17B show sequential processes for manufacturing a semiconductordevice having FinFETs with a flat-top source/drain epitaxial layeraccording to an embodiment of the present disclosure. It is understoodthat additional operations can be provided before, during, and afterprocesses shown by FIGS. 1-17B, and some of the operations describedbelow can be replaced or eliminated, for additional embodiments of themethod. The order of the operations/processes may be interchangeable. InFIGS. 1-17B, the “A” figures (FIG. 1A, 2A, . . . ) show cross sectionalviews along the Y direction, and the “B” figures (FIGS. 1B, 2B, . . . )show plan views (top views).

FIGS. 1A and 1B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 1A is a cross sectional view corresponding to lineY1-Y1 of FIG. 1B.

As shown in FIGS. 1A and 1B, a semiconductor substrate 10 is provided.In one embodiment, the substrate 10 includes a single crystallinesemiconductor layer on at least its surface portion. The substrate 10may comprise a single crystalline semiconductor material such as, butnot limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs,GaSbP, GaAsSb and InP. In one embodiment, the substrate 10 is made ofSi.

The substrate 10 may include in its surface region, one or more bufferlayers (not shown). The buffer layers can serve to gradually change thelattice constant from that of the substrate to that of the source/drainregions. The buffer layers may be formed from epitaxially grown singlecrystalline semiconductor materials such as, but not limited to Si, Ge,GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN,GaP, and InP. In a particular embodiment, the substrate 10 comprisessilicon germanium (SiGe) buffer layers epitaxially grown on the siliconsubstrate 10. The germanium concentration of the SiGe buffer layers mayincrease from 30 atomic % germanium for the bottom-most buffer layer to70 atomic % germanium for the top-most buffer layer. The substrate 10may include various regions that have been suitably doped withimpurities (e.g., p-type or n-type conductivity).

As shown in FIGS. 2A and 2B, fin structures 20 are formed over asubstrate 10. The fin structures 20 may be patterned by any suitablemethod. For example, the fin structures may be patterned using one ormore photolithography processes, including double-patterning ormulti-patterning processes. Generally, double-patterning ormulti-patterning processes combine photolithography and self-alignedprocesses, allowing patterns to be created that have, for example,pitches smaller than what is otherwise obtainable using a single, directphotolithography process. For example, in one embodiment, a dummy layeris formed over a substrate and patterned using a photolithographyprocess. Spacers are formed alongside the patterned dummy layer using aself-aligned process. The dummy layer is then removed, and the remainingspacers may then be used to pattern the fins.

In other embodiments, the fin structures can be patterned by using ahard mask pattern 22 as an etching mask. In some embodiments, the hardmask pattern 22 includes a first mask layer and a second mask layerdisposed on the first mask layer. The first mask layer is a pad oxidelayer made of a silicon oxide, which can be formed by a thermaloxidation. The second mask layer is made of silicon nitride, which isformed by chemical vapor deposition (CVD), including low pressure CVD(LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition(PVD), atomic layer deposition (ALD), or other suitable process. Thedeposited hard mask layer is patterned into a hard mask pattern 22 byusing patterning operations including photo-lithography and etching.Then, the substrate 10 is patterned by using the hard mask pattern intofin structures 20, both extending in the X direction. In FIGS. 2A and2B, two fin structures 20 are arranged in the Y direction. But thenumber of the fin structures is not limited to two, and may be one orthree or more. In some embodiments, one or more dummy fin structures areformed on both sides of the fin structures to improve pattern fidelityin the patterning operations.

The width of the upper portion of the fin structures 20 along the Ydirection is in a range from about 5 nm to about 40 nm in someembodiments, and is in a range from about 10 nm to about 20 nm in otherembodiments. The height along the Z direction of the fin structure is ina range from about 100 nm to about 200 nm in some embodiments.

FIGS. 3A and 3B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 3A is a cross sectional view corresponding to lineY1-Y1 of FIG. 3B.

After the fin structures 20 are formed, a first insulating materiallayer 29 including one or more layers of insulating material is formedover the substrate 10 so that the fin structures 20 are fully embeddedin the first insulating material layer 29. The insulating material forthe first insulating material layer 29 may include silicon oxide,silicon nitride, silicon oxynitride (SiON), SiCN, fluorine-dopedsilicate glass (FSG), or a low-K dielectric material, formed by LPCVD(low pressure chemical vapor deposition), plasma-CVD or flowable CVD orany other suitable film formation methods. In some embodiments, thefirst insulating material layer 29 is made of silicon oxide. Anannealing operation may be performed after the formation of the firstinsulating material layer 29. Then, a planarization operation, such as achemical mechanical polishing (CMP) method and/or an etch-back method,is performed such that the hard mask patterns 22 are removed and uppersurfaces of the fin structures 20 are exposed from the first insulatingmaterial layer 29 as shown in FIG. 3A.

In some embodiments, one or more fin liner layers 28 are formed over thefin structures before forming the first insulating material layer 29.The fin liner layer 28 may be made of silicon nitride or a siliconnitride-based material (e.g., SiON or SiCN).

FIGS. 4A and 4B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 4A is a cross sectional view corresponding to lineY1-Y1 of FIG. 4B.

Then, as shown in FIG. 4A, the first insulating material layer 29 isrecessed to form a first isolation insulating layer 30 so that the upperportions of the fin structures 20 are exposed. With this operation, thefin structures 20 are electrically separated from each other by thefirst isolation insulating layer 30, which is also called a shallowtrench isolation (STI). After the recess etching, the height H1 of theexposed fin structures is in a range from about 50 nm to about 100 nm insome embodiments, and is in a range from about 60 nm to about 80 nm inother embodiments.

FIGS. 5A and 5B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 5A is a cross sectional view corresponding to lineY1-Y1 of FIG. 5B.

After the isolation insulating layer 30 is formed, a dummy gatestructure 40 is formed, as shown in FIGS. 5A and 5B. The dummy gatestructure 40 includes a dummy gate dielectric layer 41 and a dummy gateelectrode layer 42. The dummy gate dielectric layer 41 includes one ormore layers of insulating material, such as a silicon oxide-basedmaterial. In one embodiment, silicon oxide formed by CVD is used. Thethickness of the dummy gate dielectric layer 41 is in a range from about1 nm to about 5 nm in some embodiments.

The dummy gate structure 40 is formed by first blanket depositing thedummy gate dielectric layer 41 over the exposed fin structures 20 andthe upper surface of the isolation insulating layer 30. A dummy gateelectrode layer 42 is then blanket deposited on the dummy gatedielectric layer 41, such that the fin structures 20 are fully embeddedin the dummy gate electrode layer 42. The dummy gate electrode layer 42includes silicon such as polycrystalline silicon (polysilicon) oramorphous silicon. In some embodiments, the dummy gate electrode layer42 is made of polysilicon. The thickness of the dummy gate electrodelayer 42 is in a range from about 100 nm to about 200 nm in someembodiments. In some embodiments, the dummy gate electrode layer 42 issubjected to a planarization operation. The dummy gate dielectric layer41 and the dummy gate electrode layer 42 are deposited using CVD,including LPCVD and PECVD, PVD, ALD, or other suitable process.Subsequently, a mask layer is formed over the dummy gate electrodelayer. The mask layer can be a resist pattern or a hard mask pattern.

Next, a patterning operation is performed on the mask layer and thedummy gate electrode layer 42 is patterned into the dummy gatestructures 40, as shown in FIGS. 5A and 5B. By patterning the dummy gatestructures, the upper portions of the fin structures 20, which are to besource/drain regions, are partially exposed on opposite sides of thedummy gate structures 40, as shown in FIG. 5B. In this disclosure, asource and a drain are interchangeably used and the structures thereofare substantially the same. In FIG. 5B, two dummy gate structures 40 areformed on two fin structures 20, respectively, and one dummy gatestructure 40 is formed over two fin structures 20. However, the layoutis not limited to FIG. 5B.

The width of the dummy gate structures 40 in the Y direction is in arange from about 5 nm to about 30 nm in some embodiments, and is in arange from about 7 nm to about 15 nm in other embodiments. A pitch ofthe dummy gate structures is in a range from about 10 nm to about 50 nmin some embodiments, and is in a range from about 15 nm to about 40 nmin other embodiments.

FIGS. 6A and 6B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 6A is a cross sectional view corresponding to lineY2-Y2 of FIG. 6B.

After the dummy gate structures 40 are formed, a blanket layer of aninsulating material for sidewall spacers 45 is conformally formed byusing CVD or other suitable methods. The blanket layer is deposited in aconformal manner so that it is formed to have substantially equalthicknesses on vertical surfaces, such as the sidewalls, horizontalsurfaces, and the top of the dummy gate structures. In some embodiments,the blanket layer is deposited to a thickness in a range from about 2 nmto about 20 nm. In one embodiment, the insulating material of theblanket layer is different from the materials of the first isolationinsulating layer and the second isolation insulating layer, and is madeof a silicon nitride-based material, such as silicon nitride, SiON,SiOCN or SiCN and combinations thereof. In some embodiments, the blanketlayer (sidewall spacers 45) is made of silicon nitride. The sidewallspacers 45 are formed on opposite sidewalls of the dummy gate structures40, by anisotropic etching, as shown in FIGS. 6A and 6B.

FIGS. 7A and 7B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 7A is a cross sectional view corresponding to lineY2-Y2 of FIG. 7B.

Subsequently, an interlayer dielectric (ILD) layer 50 is formed. Thematerials for the ILD layer 50 include compounds comprising Si, O, Cand/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, suchas polymers, may be used for the ILD layer 50. After the ILD layer 50 isformed, a planarization operation, such as CMP, is performed, so thatthe top portions of the dummy gate electrode layers of the dummy gatestructures 40 are exposed, as shown in FIG. 7A. In some embodiments, ahard mask layer (not shown) is used to pattern the dummy gate structure40, and the planarization operation removes the hard mask layer in someembodiments.

FIGS. 8A and 8B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 8A is a cross sectional view corresponding to lineY2-Y2 of FIG. 8B.

Next, as shown in FIGS. 8A and 8B, the dummy gate structures 40 areremoved, thereby forming gate spaces 48, in which the upper portions ofthe fin structures 20 are exposed, respectively. The sidewall spacers 45are not removed in some embodiments.

The ILD layer 50 protects the S/D regions of the fin structures 20during the removal of the dummy gate structures 40. The dummy gatestructures 40 can be removed using plasma dry etching and/or wetetching. When the dummy gate electrode layer is polysilicon and the ILDlayer 50 is silicon oxide, a wet etchant such as a tetramethylammoniumhydroxide (TMAH) solution can be used to selectively remove the dummygate electrode layer. The dummy gate dielectric layer is thereafterremoved using plasma dry etching and/or wet etching.

FIGS. 9A and 9B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 9A is a cross sectional view corresponding to lineY2-Y2 of FIG. 9B.

Then, a gate dielectric layer 60 is formed over the exposed finstructures 20, which are channel regions, and the surrounding areas, asshown in FIGS. 9A and 9B. In certain embodiments, the gate dielectriclayer 60 includes one or more layers of a dielectric material, such assilicon oxide, silicon nitride, or a high-k dielectric material, othersuitable dielectric material, and/or combinations thereof. Examples ofhigh-k dielectric materials include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO,HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafniumdioxide-alumina (HfO₂—Al₂O₃) alloy, other suitable high-k dielectricmaterials, and/or combinations thereof. In some embodiments, the gatedielectric layer 60 includes an interfacial layer formed between thechannel layers and the dielectric material, by using chemical oxidation.

The gate dielectric layer 60 may be formed by CVD, ALD or any suitablemethod. In one embodiment, the gate dielectric layer 60 is formed usinga highly conformal deposition process such as ALD in order to ensure theformation of a gate dielectric layer having a uniform thickness aroundeach channel layers. The thickness of the gate dielectric layer 60 is ina range from about 1 nm to about 6 nm in one embodiment.

FIGS. 10A and 10B and FIGS. 11A and 11BB show one of the various stagesof sequential processes for manufacturing a semiconductor device havingFinFETs with a flat-top source/drain epitaxial layer according to anembodiment of the present disclosure. FIG. 10A is a cross sectional viewcorresponding to line Y2-Y2 of FIG. 10B. FIG. 11A is a cross sectionalview corresponding to line Y1-Y1 of FIG. 11B.

Subsequently, a gate electrode layer 65 is formed on the gate dielectriclayer 60. The gate electrode layer 65 includes one or more layers ofconductive material, such as polysilicon, aluminum, copper, titanium,tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickelsilicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metalalloys, other suitable materials, and/or combinations thereof.

The gate electrode layer 65 may be formed by CVD, ALD, electro-plating,or other suitable method. The gate dielectric layer 60 and the electrodelayer 65 are also deposited over the upper surface of the ILD layer 50.The gate dielectric layer and the gate electrode layer formed over theILD layer 50 are then planarized by using, for example, CMP, until thetop surface of the ILD layer 50 is revealed, as shown in FIG. 10A.

In certain embodiments of the present disclosure, one or more workfunction adjustment layers (not shown) are interposed between the gatedielectric layer 60 and the gate electrode layer 65. The work functionadjustment layers are made of a conductive material such as a singlelayer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi orTiAlC, or a multilayer of two or more of these materials. For then-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSiand TaSi is used as the work function adjustment layer, and for thep-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC andCo is used as the work function adjustment layer. The work functionadjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, orother suitable process. Further, the work function adjustment layer maybe formed separately for the n-channel FET and the p-channel FET whichmay use different metal layers.

FIG. 11A shows the source/drain regions of the fin structures 20 afterthe gate electrode layer 65 is formed. As shown in FIG. 11A, thesource/drain regions of the fin structures 20 are covered by the ILDlayer 50.

FIGS. 12A and 12B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 12A is a cross sectional view corresponding to lineY1-Y1 of FIG. 12B.

As shown in FIGS. 12A and 12B, the ILD layer 50 is patterned by one ormore lithography and etching operations, thereby forming a source/drainopening 58. In the source/drain opening 58, the source/drain regions ofthe fin structure 20 are exposed.

In some embodiments, the source/drain regions of the fin structure 20are doped with appropriate dopants before or after the source/drainopening 58 is formed. In FIGS. 12A and 12B, one source/drain opening 58is formed to expose two fin structures 20. However, the configuration isnot limited to this. In some embodiments, one source/drain opening 58 isformed over only one fin structure, and in other embodiments, onesource/drain opening 58 is formed over three or more fin structures.

FIGS. 13A and 13B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 13A is a cross sectional view corresponding to lineY1-Y1 of FIG. 13B.

After the source/drain opening 58 is formed and the source/drain regionsof the fin structures 20 are exposed, one or more source/drain epitaxialsemiconductor layers 70 are formed over the fin structures 20 as shownin FIGS. 13A and 13B. In some embodiments, the source/drain epitaxiallayer 70 includes Ge doped with phosphorous (Ge:P) or Si_(1-x)Ge_(x)doped with P (SiGe:P), where 0.3<x<1, for n-type FETs. In certainembodiments, 0.3<x, or 0.5<x<0.8.

In some embodiments, an amount of P in the Ge:P layer or the SiGe:Player is in a range from about 1×10¹⁹ atoms/cm³ to 1×10²⁰ atoms/cm³. Inother embodiments, the amount of P is in a range from about 2×10¹⁹atoms/cm³ to 8×10¹⁹ atoms/cm³. In other embodiments, boron (B) is dopedfor p-type FETs, in a range from about 1×10¹⁹ atoms/cm³ to 1×10²⁰atoms/cm³, or in a range from about 2×10¹⁹ atoms/cm³ to 8×10¹⁹atoms/cm³.

The Ge:P layer can be epitaxially formed on the source/drain regions ofthe fin structures 20 by using a metal-organic CVD (MOCVD), molecularbeam epitaxy (MBE), ALD or any other film formation methods. In someembodiments, a Ge₂H₆ gas is used as a source gas of Ge. In someembodiments, a Si₂H₆ gas is used as a source gas of Si. In certainembodiments, instead of or, in addition to, Ge₂H₆ and/or Si₂H₆, GeH₄and/or SiH₄ is used. One or more inert gas, such as H₂, He, Ar and/orN₂, is used as a dilution gas.

During the epitaxial formation of the Ge:P layer or the SiGe:P layer, asubstrate temperature is maintained at a range from about 350° C. toabout 410° C. in some embodiments. The substrate temperature is atemperature of a hot plate or a wafer holder/stage. In otherembodiments, the substrate temperature is in a range from about 380° C.to about 400° C. When a Ge₂H₆ gas and/or a Si₂H₆ gas is used, it ispossible to epitaxially form the Ge or SiGe layer 70 at a relatively lowtemperature of less than about 400° C. The source/drain epitaxial layer70 can be selectively formed from the semiconductor fin structures 20,and is not formed on the upper surface of the ILD layer 50. A doping gasis PH₃ for phosphorous, AsH₃ for arsenic or B₂H₆ for boron.

The source/drain epitaxial layer 70 is formed such that a thickness H₂of the source/drain epitaxial layer 70 above the fin structures is in arange from about 10 nm to about 100 nm in some embodiments, and is in arange from about 20 nm to about 60 nm in other embodiments. As shown inFIG. 13A, the source/drain epitaxial layer 70 as deposited has an unevensurface. In some embodiments, the source/drain epitaxial layer 70 has ahighest portion and a lowest portion measured from the substrate 10, andthe difference between the highest portion and the lowest portion H₃ isin a range from about from about 10 nm to about 100 nm in someembodiments, and is in a range from about 20 nm to about 60 nm in otherembodiments. The lowest portion is located between the two finstructures in some embodiments, and is located at the interface betweenthe source/drain epitaxial layer 70 and the ILD layer 50 in otherembodiments. Further, as shown in FIG. 13A, no void is formed in thesource/drain opening 58 between the source/drain epitaxial layer 70 andthe isolation insulating layer 30 and between the source/drain epitaxiallayer 70 and the ILD layer 50.

FIGS. 14A and 14B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 14A is a cross sectional view corresponding to lineY1-Y1 of FIG. 14B.

After the source/drain epitaxial layer 70 is formed, a thermal annealingoperation is optionally performed to flatten the surface of thesource/drain epitaxial layer 70, as shown in FIGS. 14A and 14B. Theannealing operation is performed by heating the substrate at atemperature in a range from about 410° C. to about 470° C. in someembodiment, and in a range from about 440° C. to about 460° C. in otherembodiments. The annealing operation is performed for a time duration ina range from about 100 sec to about 500 sec in some embodiments, and ina range from about 250 sec to 350 sec in other embodiments. In someembodiments, the annealing operation is performed in the samemanufacturing apparatus, in particular, in the same process chamber asthe process of forming the source/drain epitaxial layer 70. In certainembodiments, after the process gas(es) for the epitaxial growth is/arestopped, and then the substrate temperature is increased to theannealing temperature. Thus, the annealing operation is performedwithout exposing the substrate (the source/drain epitaxial layer) to theatmosphere, in particular to an oxygen containing atmosphere. In someembodiments, during the annealing operation, an inert gas, such as H₂,He, Ar and/or N₂, is supplied. By the annealing operation, the uppersurface of the source/drain epitaxial layer 70 becomes substantiallyflat. In other embodiments, a planarization operation, such as anetch-back operation or a chemical mechanical polishing operation, isemployed to flatten the upper surface of the source/drain epitaxiallayer 70.

In certain embodiments, a laser annealing operation is performed toflatten the source/drain epitaxial layer 70. In such a case, a laserbeam is selectively applied only to the source/drain area avoiding thegate structure. In some embodiments, the source/drain epitaxial layer isheated to about 800° C. to about 1000° C. in some embodiments. The timeduration of applying the laser to the source/drain region is in a rangefrom about 0.1 nsec to 1000 nsec in some embodiments, and is in a rangefrom about 1 nsec to 100 nsec in other embodiments.

In some embodiments, the distance H4 between the top of the finstructure 20 and the upper surface of the source/drain epitaxial layer70 is in a range from about 5 nm to about 90 nm in some embodiments, andis in a range from about 10 nm to about 50 nm in other embodiments. Thethickness H5 of the source/drain epitaxial layer 70 from the uppersurface of the isolation insulating layer 30 is in a range from about 55nm to about 190 nm in some embodiments, and is in a range from about 70nm to about 130 nm in other embodiments.

In some embodiments, the upper surface of the source/drain epitaxiallayer 70 is not completely flat. As shown in FIGS. 14C and 14D, thethickness (flatness) variation D1, which is the difference between themaximum thickness Hmax and the minimum thickness Hmin of thesource/drain epitaxial layer 70, is less than about 5 nm in someembodiments. In certain embodiments, the variation D1 is more than 0 nmor more than about 0.2 nm. In other embodiment, the variation D1 is in arange from about 0.3 nm to about 3 nm. In some embodiments, the uppersurface of the source/drain epitaxial layer has a convex shape, as shownin FIG. 14C, and the maximum thickness is located at the interfacebetween the source/drain epitaxial layer and the ILD layer 50. Incertain embodiments, the minimum thickness is located between the twofin structures or at the other interface between the source/drainepitaxial layer and the ILD layer 50. In other embodiments, the uppersurface of the source/drain epitaxial layer has a wavy shape, as shownin FIG. 14D. In some embodiments, by adjusting epitaxial growthconditions, the upper surface of the source/drain epitaxial layer 70 ismade flat without an additional heating operation as set forth above.

FIGS. 15A and 15B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 15A is a cross sectional view corresponding to lineY1-Y1 of FIG. 15B.

After the heating (annealing) process, an interfacial layer 75 is formedover the source/drain epitaxial layer 70, as shown in FIGS. 15A and 15B.In some embodiments, the interfacial layer 75 is made of a semiconductormaterial. The semiconductor material for the interfacial layer includesSi or Si_(1-y)Ge_(y), where 0<y<0.3. In some embodiments, phosphorous(P) and/or arsenic (As) is doped in the semiconductor interfacial layer75. In other embodiments, boron (B) is doped. The doping amount in theinterfacial semiconductor layer 75 is in a range from about 1×10²⁰atoms/cm³ to 1×10²¹ atoms/cm³ in some embodiments, and is in a rangefrom about 2×10²⁰ atoms/cm³ to 8×10²⁰ atoms/cm³ in other embodiments. Incertain embodiments, Si doped with P is used as the interfacialsemiconductor layer 75. In some embodiments, the interfacialsemiconductor layer 75 is non-single crystalline, and is amorphousand/or poly crystalline.

The interfacial semiconductor layer 75 can be formed on the source/drainepitaxial layer by using a metal-organic CVD (MOCVD), ALD or any otherfilm formation methods. In some embodiments, one or more of SiH₄, Si₂H₆,Si₃H₈, Si₄H₁₀, GeH₄ and Ge₂H₆ are used as a source gas. In certainembodiments, Si₃H₈ and PH₃ are used to form a Si:P layer. During theepitaxial formation of the interfacial semiconductor layer 75, asubstrate temperature is maintained at a range from about 410° C. toabout 470° C. in some embodiments. In other embodiments, the substratetemperature is in a range from about 440° C. to about 460° C. In certainembodiments, the substrate temperature for forming the interfacialsemiconductor layer is the same or substantially the same as that in theannealing operation. In other embodiments, a change in the substratetemperature between the annealing operation and the formation of theinterfacial layer is within ±10° C. (substantially the same).

The thickness H6 of the interfacial semiconductor layer 75 is in a rangefrom about 5 nm to about 50 nm in some embodiments, and is in a rangefrom about 10 nm to 30 nm in other embodiments. As shown in FIG. 15A, insome embodiments, the interfacial semiconductor layer 75 is also formedon the ILD layer 50. In other words, the interfacial semiconductor layer75 is conformally formed.

In some embodiments, the formation of the interfacial layer 75 isperformed in the same manufacturing apparatus, in particular, in thesame process chamber as the annealing operation. In certain embodiments,after the intended annealing time passes, the process gas for theinterfacial layer 75 is supplied. Thus, the formation of the interfaciallayer 75 is performed without exposing the substrate (the flattenedsource/drain epitaxial layer) to the atmosphere, in particular to anoxygen containing atmosphere.

FIGS. 16A and 16B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 16A is a cross sectional view corresponding to lineY1-Y1 of FIG. 16B.

In some embodiments, an ion implantation operation 72 is performed toimplant additional dopant to the source/drain epitaxial layer 70, asshown in FIGS. 16A and 16B. In some embodiments, P and/or As areimplanted. In other embodiments, B (BF₂) is implanted. In someembodiments, a laser annealing operation is performed to activate thedopants (doped impurities) in the source/drain epitaxial layer 70. Insuch a case, a laser beam is selectively applied only to thesource/drain area, avoiding the gate structure. In some embodiments, thesource/drain epitaxial layer is heated to about 800° C. to about 1000°C. in some embodiments. The laser annealing may be performed withoutperforming the ion implantation operation 72.

FIGS. 17A and 17B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to an embodiment of the presentdisclosure. FIG. 17A is a cross sectional view corresponding to lineY1-Y1 of FIG. 17B.

After the interfacial layer 75 is formed, a conductive contact 80 isformed, as shown in FIGS. 17A and 17B. One or more layers of conductivematerials are formed in the remaining portion of the contact opening 58.One or more layers of conductive materials are formed in and over thecontact openings and then a planarization operation, such as a CMPoperation, is performed to form contact 80, as shown in FIGS. 17A and17B. In some embodiments, the contact 80 includes a liner layer 82 and abody layer 82. The liner layer is a barrier layer and/or a glue(adhesion) layer. In some embodiments, a Ti layer is formed on theinterfacial layer 75 and a TiN or TaN layer is formed on the Ti layer,as the liner layer 82. The body layer 84 includes one or more layers ofCo, Ni, W, Ti, Ta, Cu and Al, or any other suitable material.

As shown in FIGS. 17A and 17B, the conductive contact 80 is in contactwith only the upper surface of the source/drain epitaxial layer 70 viathe interfacial semiconductor layer 75, and thus does not form awrap-around contact structure in which side faces of a source/drainregion and/or a source/drain epitaxial layer are covered by theconductive contact. The ILD layer 50 has a contact opening (58), and alower portion of the contact opening is filled by the source/drainepitaxial layer 70 and an upper portion of the contact opening is filledby the interfacial semiconductor layer 75 and the conductive contact 80.Further, no void is formed between the source/drain regions of the finstructures 20. In some embodiments, the side faces of the source/drainepitaxial layer 70 and the side faces of the conductive contact 80 arein direct contact with an inner wall of the opening of the ILD layer 50.

FIGS. 18A and 18B show one of the various stages of sequential processesfor manufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to another embodiment of thepresent disclosure. FIGS. 18A and 18B are top views after thesource/drain epitaxial layer is formed.

When the contact opening 58 is formed as shown in FIGS. 12A and 12B, theshape of the contact opening in a top (plan) view has rounded corners insome embodiments as shown in FIG. 18A. In certain embodiments, when theliner side (e.g., along the Y direction) of the opening 58 is small, theshape of the opening 58 is oval as shown in FIG. 18B. Thus, thesource/drain epitaxial layer 70 has a cylindrical shape with a top viewbeing oval, circular or polygonal with round corners, into which the finstructures 20 penetrate from the bottom.

FIGS. 19A and 19B show the various stages of sequential processes formanufacturing a semiconductor device having FinFETs with a flat-topsource/drain epitaxial layer according to another embodiment of thepresent disclosure. FIGS. 19A and 19B are cross sectional viewscorresponding to line Y1-Y1 of FIG. 19B.

When the contact opening 58 is formed as shown in FIGS. 12A and 12B, apart of the side faces of the ILD layer 50 forming the opening is overetched to form a concave portion 59, as shown in FIG. 19A. The concaveportion 59 is formed due to a change in etching condition (e.g., gases,powers, etc) during the etching of the ILD layer 50 to form the opening58. Depending on the timing of the change, the location of the concaveportion 59 changes. In some embodiments, the concave portion 59 isformed at a level between the top of the fin structure 20 and the uppersurface of the isolation insulating layer 30, as shown in FIG. 19A. Inother embodiments, the concave portion 59 is formed at a level of thetop of the fin structure 20, and in certain embodiments, the concaveportion 59 is formed at a level higher than the top of the fin structure20. After the source/drain epitaxial layer 70 is formed, thesource/drain epitaxial layer has a convex portion corresponding to theconcave portion 59, as shown in FIG. 19B. The depth (maximum depth) T1of the convex portion 59 from the side face of the opening is in a rangefrom about 2 nm to about 30 nm in some embodiments. In some embodiments,two or more convex portions 59 are formed at different levels of oneside face of the opening.

FIG. 20A shows a cross sectional view of a semiconductor device havingFinFETs with a flat-top source/drain epitaxial layer according toanother embodiment of the present disclosure. In this embodiment, asilicide layer 78 is formed between the interfacial semiconductor layer75 and the contact 80. In some embodiments, the silicide layer 78includes one or more of WSi, CoSi, NiSi, TiSi, MoSi and TaSi.

FIG. 20B shows a cross sectional view of a semiconductor device havingFinFETs with a flat-top source/drain epitaxial layer according toanother embodiment of the present disclosure. In this embodiment, thesource/drain region 24 is made of a different material than thesubstrate 10. After the contact opening 58 is formed as shown in FIGS.12A and 12B, the source/drain region of the fin structures 20 arerecessed to or below the level of the upper surface of the isolationinsulating layer 30. Then, by using an epitaxial growth method, asource/drain semiconductor region 24 is formed over the recessed finstructures. In some embodiments, when the substrate 10 is Si, thesource/drain semiconductor region 24 is Ge or Si_(1-z)Ge_(z), where0.3<z<1. In other embodiments, two or more semiconductor layers are usedas the source/drain semiconductor region 24.

FIGS. 20C and 20D show cross sectional views of a semiconductor devicehaving FinFETs with a flat-top source/drain epitaxial layer according toother embodiments of the present disclosure. In FIG. 20C, only one finstructure (source/drain region) 20 is disposed in the opening 58 and iscovered by the source/drain epitaxial layer 70. In FIG. 20D, three finstructures (source/drain regions) 20 are disposed in the opening 58 andare covered by the source/drain epitaxial layer 70. The number of thefin structures in the opening 58 can be more than three and may be up to10.

FIGS. 21A-24B show sequential processes for manufacturing asemiconductor device having FinFETs with a flat-top source/drainepitaxial layer according to another embodiment of the presentdisclosure. It is understood that additional operations can be providedbefore, during, and after processes shown by FIGS. 21-24B, and some ofthe operations described below can be replaced or eliminated, foradditional embodiments of the method. The order of theoperations/processes may be interchangeable.

As shown in FIGS. 21A and 21B, a channel semiconductor layer 160 isepitaxially formed on the substrate 10. FIG. 21A is a cross sectionalview corresponding to line Y1-Y1 of FIG. 21B. In some embodiments, thesubstrate 10 is Si, and the channel semiconductor layer 160 is Ge orSi_(1-z)Ge_(z), where 0.3<z<1. In some embodiments, a buffersemiconductor layer is formed between the substrate 10 and the channelsemiconductor layer 160.

By using the similar operations explained with respect to FIGS. 2A-4B,fin structures 162 protruding from the isolation insulating layer 30 areformed, as shown in FIGS. 22A and 22B. FIG. 22A is a cross sectionalview corresponding to line Y1-Y1 of FIG. 22B.

By using the similar operations explained with respect to FIGS. 5A-11B,gate structures 65 are formed, as shown in FIGS. 23A and 23B. FIG. 23Ais a cross sectional view corresponding to line Y2-Y2 of FIG. 23B.

By using the similar operations explained with respect to FIGS. 12A-17B,conductive contacts 80 are formed, as shown in FIGS. 24A and 24B. FIG.24A is a cross sectional view corresponding to line Y1-Y1 of FIG. 24B.In some embodiments, the source/drain region of the fin structure 162 isSi_(1-z)Ge_(z), where 0.3<z<1, and the source/drain epitaxial layer 70is Ge or Si_(1-x)Ge_(x), where z<x, doped with P and/or As.

FIGS. 25A-34B show sequential processes for manufacturing asemiconductor device having GAA FETs with a flat-top source/drainepitaxial layer according to another embodiment of the presentdisclosure. It is understood that additional operations can be providedbefore, during, and after processes shown by FIGS. 25A-34B, and some ofthe operations described below can be replaced or eliminated, foradditional embodiments of the method. The order of theoperations/processes may be interchangeable.

FIGS. 25A-26B show various stages of sequential processes formanufacturing a semiconductor device having a GAA FET with a flat-topsource/drain epitaxial layer according to another embodiment of thepresent disclosure. FIGS. 25A and 26A are cross sectional viewscorresponding to line Y1-Y1 of FIGS. 25B and 26B.

As shown in FIG. 25A, a buffer semiconductor layer 127 is formed over asubstrate 10. Then, first semiconductor layers 120 and secondsemiconductor layer 125 are alternately stacked over the buffer layer127 as shown in FIGS. 26A and 26B.

In some embodiments, the substrate 10 is Si, the first semiconductorlayers 120 are Si, and the buffer semiconductor layer 127 and secondsemiconductor layer 125 are Si_(1-z)Ge_(z), where 0.2<z<0.7. In otherembodiments, the substrate 10 is Si, the first semiconductor layers 120are Ge or Si_(1-x)Ge_(x), where 0.5<x<1, and the buffer semiconductorlayer 127 and second semiconductor layer 125 are Si_(1-z)Ge_(z), where0.2<z<0.7 and z<x. In other embodiments, the semiconductor material ofthe buffer layer 127 and that of the second semiconductor layer aredifferent. The buffer semiconductor layer 127, the first semiconductorlayer 120 and the second semiconductor layer 125 are epitaxially formedby using CVD, MBE, ALD or any other suitable methods. In someembodiments, no buffer semiconductor layer 127 is formed.

By using the similar operations explained with respect to FIGS. 2A-4B,fin structures 121 protruding from the isolation insulating layer 30 areformed, as shown in FIGS. 27A and 27B. FIG. 27 is a cross sectional viewcorresponding to line Y1-Y1 of FIG. 27B.

As shown in FIG. 27A, the fin structures 121 include multiple layers ofthe first semiconductor layers 120 and the second semiconductor layers125 alternately stacked. In some embodiments, the thickness of thebuffer semiconductor layer 127 is greater than the thickness of each ofthe first semiconductor layers 120. Although FIG. 27A shows three firstsemiconductor layers 120 and four second semiconductor layers 125, thenumber of the first and second semiconductor layer can be two, three ormore than four and up to ten.

By using the similar operations explained with respect to FIGS. 5A-8B,gate spaces 48 are formed, in which the upper portions of the finstructures 121 are exposed, respectively, as shown in FIGS. 28A and 28B.FIG. 28A is a cross sectional view corresponding to line Y1-Y1 of FIG.28B. In some embodiments, a part of the buffer semiconductor layer 127is exposed in the opening 48. In other embodiments, the entire buffersemiconductor layer 127 is exposed, and in certain embodiments, thebuffer semiconductor layer 127 is not exposed in the opening 48.

Then, the buffer semiconductor layer 127 and the second semiconductorlayers 125 are removed in the gate opening 48, as shown in FIGS. 29A and29B. FIG. 29A is a cross sectional view corresponding to line Y1-Y1 ofFIG. 29B. The second semiconductor layers 125 can be selectively removedusing a wet etchant such as, but not limited to, ammonium hydroxide(NH₄OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH) solution. Thus,semiconductor wires are formed of the first semiconductor layers 120.

Then, by using the similar operations explained with respect to FIGS.9A-10B, gate structures 65 are formed, as shown in FIGS. 30A and 30B.FIG. 30A is a cross sectional view corresponding to line Y2-Y2 of FIG.30B.

Further, by using the similar operations explained with respect to FIGS.11A-12B, a source/drain opening 58 is formed by patterning the ILD layer50 using one or more lithography and etching operations, as shown inFIGS. 31A and 31B. FIG. 31A is a cross sectional view corresponding toline Y1-Y1 of FIG. 31B. In the opening 58, the source/drain regions ofthe fin structure 121 are exposed.

Then, the buffer semiconductor layer 127 and the second semiconductorlayers 125 are removed in the source/drain opening 58, as shown in FIGS.32A and 32B. FIG. 32A is a cross sectional view corresponding to lineY1-Y1 of FIG. 32B. The second semiconductor layers 125 can beselectively removed using a wet etchant such as, but not limited to,ammonium hydroxide (NH₄OH), tetramethylammonium hydroxide (TMAH),ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH)solution.

Subsequently, by using the similar operations explained with respect toFIGS. 13A-14B, a source/drain epitaxial layer 70 is formed, as shown inFIGS. 33A and 33B. FIG. 33A is a cross sectional view corresponding toline Y1-Y1 of FIG. 33B. As shown in FIG. 33A, the source/drain epitaxiallayer 70 wraps around the source/drain region of the first semiconductorlayers 121. No void is formed in the source/drain opening 58 by thesource/drain epitaxial layer 70.

Further, by using the similar operations explained with respect to FIGS.17A-17B, a interfacial layer 75 and a conductive contact 80 are formed,as shown in FIGS. 34A and 34B. FIG. 34A is a cross sectional viewcorresponding to line Y1-Y1 of FIG. 34B.

It is understood that the FinFETs and GAA FETs undergo further CMOSprocesses to form various features such as contacts/vias, interconnectmetal layers, dielectric layers, passivation layers, etc.

In the foregoing embodiments, gate structures are first formed and thena source/drain epitaxial layer is formed. In other embodiments, thesource/drain epitaxial layer and the interfacial semiconductor layer areformed while dummy gate structures are maintained, and then the gatestructures are formed be removing the dummy gate structures. In such acase, one or more dielectric or other layers are formed after theinterfacial semiconductor layer is formed, and these layers arepatterned to form the conductive contact.

FIGS. 35A-36B show simulation results of contact resistance. As shown inFIG. 35A, which is a top (plan) view of a structure used in thesimulation. Two contacts 280 are disposed over four groups of nano wires280. The two contacts 280 are separated by a contact spacing CT. Threedifferent contact structures shown in FIGS. 35B (structure B), 35C(structure C) and 35D (structure D) are tested. In the structures B-D,nine nano wires 220 made of Ge are stacked in the vertical direction,and a source/drain epitaxial layer 270 made of Ge:P surrounds the nanowires. Further, contact 280 is formed in contact with the source/drainepitaxial layer 270. In structure B, which corresponds to an ideal case,the contact 280 wraps around the source/drain epitaxial layer 270 with acontact resistance of 2×10⁻¹⁹ Ωcm² for all at three faces (the top andtwo sides). In structure C, which corresponds to a manufactured GAA FETcase by a current production method, the contact 280 wraps around thesource/drain epitaxial layer 270 with a contact resistance of 2×10⁻¹⁹Ωcm² only for the top face and with a contact resistance of 1×10⁻¹⁷ Ωcm²for the two side faces, for example. Due to process conditions or someother factors, the contact resistance of the side faces becomes higherthan that of the top face. For example, when a laser annealing isutilized, only the top of the epitaxial layer is effectively treated bythe laser to decrease the contact resistance. In structure D, whichcorresponds to embodiments of the present disclosure, the contact 280 isformed on the top face of the source/drain epitaxial layer 270 with acontact resistance of 2×10⁻¹⁹ Ωcm².

FIGS. 36A and 36B show calculated total resistance between two contacts280. The total resistance includes a resistance of the nano wires andthe contact resistance (two components, left and right). FIG. 36A is acase in which the pitch P of the group of nano wires is 24 nm, and FIG.36B is a case in which the pitch P of the group of nano wires is 48 nm.As shown in FIGS. 36A and 36B, the structure D, which corresponds to theembodiments of the present disclosure, shows lower contact resistancevalues than the structure C, which corresponds to the manufactured case.

The various embodiments or examples described herein offer severaladvantages over the existing art. For example, in the presentdisclosure, by using a flat-top source/drain epitaxial layer with aconductive contact contacting on the flat-top, it is possible to reducea contact resistance at a source/drain region of a FinFET or a GAA FET.Further, by providing a larger volume of the source/drain epitaxiallayer than a wrap-around contact structure, it is possible to provide ahigher amount of stress from the source/drain epitaxial layer to achannel region of FETs.

It will be understood that not all advantages have been necessarilydiscussed herein, no particular advantage is required for allembodiments or examples, and other embodiments or examples may offerdifferent advantages.

In accordance with one aspect of the present disclosure, in a method ofmanufacturing a semiconductor device, an opening is formed in aninterlayer dielectric layer such that a source/drain region is exposedin the opening. A first semiconductor layer is formed to fully cover theexposed source/drain region within the opening. A heating process isperformed to make an upper surface of the first semiconductor layersubstantially flat. A conductive contact layer is formed over the firstsemiconductor layer. In one or more of the foregoing or followingembodiments, after the heating process is performed and before theconductive contact is formed, a second semiconductor layer is formedover the first semiconductor layer and an upper surface of theinterlayer dielectric layer. In one or more of the foregoing orfollowing embodiments, the first semiconductor layer is Ge orSi_(1-x)Ge_(x), where 0.3<x<1. In one or more of the foregoing orfollowing embodiments, the first semiconductor layer is doped withphosphorous. In one or more of the foregoing or following embodiments,the first semiconductor layer is epitaxially formed at a substratetemperature in a range from 350° C. to 410° C., and the heating processis performed at the substrate temperature in a range from 410° C. to470° C. In one or more of the foregoing or following embodiments, thesecond semiconductor layer is Si or Si_(1-y)Ge_(y), where 0<y<0.3, andthe second semiconductor layer is formed at a substrate temperature in arange from 410° C. to 470° C. In one or more of the foregoing orfollowing embodiments, the second semiconductor layer is amorphous orpolycrystalline. In one or more of the foregoing or followingembodiments, the second semiconductor layer is doped with phosphorous.In one or more of the foregoing or following embodiments, no void isformed at a bottom or sides of the first semiconductor layer. In one ormore of the foregoing or following embodiments, side faces of the firstsemiconductor layer and side faces of the conductive contact are incontact with an inner wall of the opening.

In accordance with another aspect of the preset disclosure, in a methodof manufacturing a semiconductor device, an opening is formed in aninterlayer dielectric layer such that a source/drain region of a finstructure is exposed in the opening. The source/drain region of the finstructure protrudes from an isolation insulating layer. A firstsemiconductor layer is formed by an epitaxial growth to fully cover theexposed source/drain region within the opening. A heating process isperformed to reflow the first semiconductor layer. A secondsemiconductor layer is formed over the first semiconductor layer. Aconductive contact layer is formed on the second semiconductor layer. Inone or more of the foregoing or following embodiments, after the heatingprocess is performed, a thickness variation of the first semiconductorlayer in the opening is less than or equal to 5 nm. In one or more ofthe foregoing or following embodiments, after the heating process isperformed, the thickness variation of the first semiconductor layer inthe opening is more than or equal to 0.2 nm. In one or more of theforegoing or following embodiments, after the second semiconductor layeris formed and before the conductive contact is formed, the first andsecond semiconductor layers are annealed. In one or more of theforegoing or following embodiments, the annealing operation is performedby a laser annealing method. In one or more of the foregoing orfollowing embodiments, the forming the first semiconductor layer, theperforming the heating process and the forming the second semiconductorlayer are performed in a same manufacturing apparatus. In one or more ofthe foregoing or following embodiments, the heating process and theforming the second semiconductor layer are performed at a same substratetemperature. In one or more of the foregoing or following embodiments, agrowth rate of the first semiconductor layer is in a range from 5 nm/minto 15 nm/min.

In accordance with another aspect of the present disclosure, in a methodof manufacturing a semiconductor device, an opening is formed in aninterlayer dielectric layer such that source/drain regions are exposedin the opening. A first semiconductor layer is formed to fully cover theexposed source/drain regions within the opening. A heating process isperformed to make an upper surface of the first semiconductor layersubstantially flat. A conductive contact layer is formed over the firstsemiconductor layer. In one or more of the foregoing or followingembodiments, the source/drain regions are (i) portions of multiple finsprotruding from an isolation insulating layer, or (ii) portions ofsemiconductor wires horizontally extending over the isolation insulatinglayer.

In accordance with one aspect of the present disclosure, a semiconductordevice includes a gate structure disposed over a channel semiconductorlayer, a source/drain region disposed on a side of the channelsemiconductor layer, a first epitaxial semiconductor layer covering thesource/drain region, a conductive contact disposed over the firstepitaxial semiconductor layer, and a dielectric layer having an opening,a lower portion of which is filled by the first epitaxial semiconductorlayer and an upper portion of which is filled by the conductive contact.In one or more of the foregoing or following embodiments, thesemiconductor device further includes a second semiconductor layerdisposed in the opening between the first epitaxial semiconductor layerand the conductive contact and between the dielectric layer and theconductive contact. In one or more of the foregoing or followingembodiments, the first epitaxial semiconductor layer is Ge orSi_(1-x)Ge_(x), where 0.3<x<1. In one or more of the foregoing orfollowing embodiments, the first epitaxial semiconductor layer is dopedwith phosphorous in an amount of 1×10¹⁹ atoms/cm³ to 1×10²⁰ atoms/cm³.In one or more of the foregoing or following embodiments, the secondsemiconductor layer is Si or Si_(1-y)Ge_(y), where 0<y<0.3. In one ormore of the foregoing or following embodiments, the second semiconductorlayer is amorphous or polycrystalline. In one or more of the foregoingor following embodiments, the second semiconductor layer is doped withphosphorous in an amount of 1×10²⁰ atoms/cm³ to 1×10²¹ atoms/cm³. In oneor more of the foregoing or following embodiments, the source/drainregion is Ge or Si_(1-z)Ge_(z), where 0.3<z<1. In one or more of theforegoing or following embodiments, no void is formed at a bottom orsides of the first epitaxial semiconductor layer. In one or more of theforegoing or following embodiments, side faces of the first epitaxialsemiconductor layer and side faces of the conductive contact are incontact with an inner wall of the opening. In one or more of theforegoing or following embodiments, a thickness variation of the firstepitaxial semiconductor layer in the opening is less than or equal to 5nm. In one or more of the foregoing or following embodiments, thethickness variation of the first epitaxial semiconductor layer in theopening is more than or equal to 0.2 nm. In one or more of the foregoingor following embodiments, the first epitaxial semiconductor layer isdoped with boron in an amount of 1×10¹⁹ atoms/cm³ to 1×10²⁰ atoms/cm³.In one or more of the foregoing or following embodiments, the firstepitaxial semiconductor layer is doped with gallium in an amount of1×10¹⁹ atoms/cm³ to 1×10²⁰ atoms/cm³.

In accordance with another aspect of the present disclosure, asemiconductor device includes channel semiconductor layers disposed overa substrate, source/drain regions disposed on sides of the channelsemiconductor layers, a gate structure disposed over at least one of thechannel semiconductor layers, a first semiconductor layer covering thesource/drain regions, a second semiconductor layer made of a differentmaterial than the first semiconductor layer and disposed on the firstsemiconductor layer, a conductive contact disposed over the secondsemiconductor layer, and a dielectric layer having an opening, a lowerportion of which is filled by the first epitaxial semiconductor layerand an upper portion of which is filled by the second semiconductorlayer and the conductive contact. In one or more of the foregoing orfollowing embodiments, a thickness variation of the first epitaxialsemiconductor layer in the opening is less than or equal to 5.0 nm. Inone or more of the foregoing or following embodiments, a thicknessvariation of the first epitaxial semiconductor layer in the opening isless than or equal to 3.0 nm. In one or more of the foregoing orfollowing embodiments, the thickness variation of the first epitaxialsemiconductor layer in the opening is more than or equal to 0.2 nm. Inone or more of the foregoing or following embodiments, no void is formedbetween the source/drain regions.

In accordance with another aspect of the present disclosure, asemiconductor device includes semiconductor wires arranged in a verticaldirection over a substrate, and having channel regions and source/drainregions, respectively, a gate structure surrounding the channel regions,a first semiconductor layer covering the source/drain regions, a secondsemiconductor layer made of a different material than the firstsemiconductor layer and disposed on the first semiconductor layer, and aconductive contact disposed over the second semiconductor layer. Athickness variation of the first epitaxial semiconductor layer is lessthan or equal to 5.0 nm.

The foregoing outlines features of several embodiments or examples sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodiments orexamples introduced herein. Those skilled in the art should also realizethat such equivalent constructions do not depart from the spirit andscope of the present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method of manufacturing a semiconductor device,the method comprising: forming a fin structure, in which firstsemiconductor layers and second semiconductor layers are alternatelystacked over a bottom fin structure; forming an interlayer dielectric(ILD) layer over the fin structure; forming an opening in the ILD layersuch that a source/drain region of the fin structure is exposed in theopening; removing the first semiconductor layers from the source/drainregion of the fin structure is exposed in the opening; forming a thirdsemiconductor layer to fully wrap around each of the first semiconductorlayers within the opening; performing a heating process to make an uppersurface of the third semiconductor layer substantially flat; and forminga conductive contact layer over the first semiconductor layer.
 2. Themethod of claim 1, further comprising, after the heating process isperformed and before the conductive contact is formed, forming a fourthsemiconductor layer over the third semiconductor layer and an uppersurface of the interlayer dielectric layer.
 3. The method of claim 1,wherein the third semiconductor layer is Ge or Si_(1-x)Ge_(x), where0.3<x<1.
 4. The method of claim 3, wherein the third semiconductor layeris doped with phosphorous.
 5. The method of claim 3, wherein: the thirdsemiconductor layer is epitaxially formed at a substrate temperature ina range from 350° C. to 410° C., and the heating process is performed atthe substrate temperature in a range from 410° C. to 470° C.
 6. Themethod of claim 3, wherein: the fourth semiconductor layer is Si orSi_(1-y)Ge_(y), where 0<y<0.3, and the fourth semiconductor layer isformed at a substrate temperature in a range from 410° C. to 470° C. 7.The method of claim 6, wherein the fourth semiconductor layer isamorphous or polycrystalline.
 8. The method of claim 6, wherein thefourth semiconductor layer is doped with phosphorous.
 9. The method ofclaim 1, wherein no void is formed at a bottom or sides of the thirdsemiconductor layer.
 10. The method of claim 1, wherein side faces ofthe third semiconductor layer and side faces of the conductive contactare in contact with an inner wall of the opening.
 11. A method ofmanufacturing a semiconductor device, the method comprising: forming afin structure, in which first semiconductor layers and secondsemiconductor layers are alternately stacked over a bottom finstructure, a source/drain region of the fin structure protruding from anisolation insulating layer; forming an interlayer dielectric (ILD) layerover the fin structure; forming an opening in the ILD layer such that asource/drain region of the fin structure is exposed in the opening;removing the first semiconductor layers from the source/drain region ofthe fin structure is exposed in the opening; forming a thirdsemiconductor layer to fully wrap around each of the first semiconductorlayers within the opening; performing a heating process to reflow thethird semiconductor layer; forming a fourth semiconductor layer over thethird semiconductor layer; and forming a conductive contact layer on thefourth semiconductor layer.
 12. The method of claim 11, wherein afterthe heating process is performed, a thickness variation of the thirdsemiconductor layer in the opening is less than or equal to 5 nm. 13.The method of claim 12, wherein after the heating process is performed,the thickness variation of the third semiconductor layer in the openingis more than or equal to 0.2 nm.
 14. The method of claim 11, furthercomprising, after the fourth semiconductor layer is formed and beforethe conductive contact is formed, annealing the third and fourthsemiconductor layers.
 15. The method of claim 14, wherein the annealingoperation is performed by a laser annealing method.
 16. The method ofclaim 11, wherein the forming the third semiconductor layer, theperforming the heating process and the forming the fourth semiconductorlayer are performed in a same manufacturing apparatus.
 17. The method ofclaim 11, wherein the heating process and the forming the fourthsemiconductor layer are performed at a same substrate temperature. 18.The method of claim 11, wherein a growth rate of the third semiconductorlayer is in a range from 5 nm/min to 15 nm/min.
 19. A method ofmanufacturing a semiconductor device, the method comprising: forming afin structure, in which first semiconductor layers and secondsemiconductor layers are alternately stacked over a bottom finstructure, a source/drain region of the fin structure protruding from anisolation insulating layer; forming an interlayer dielectric (ILD) layerover the fin structure; forming an opening in the ILD layer such that asource/drain region of the fin structure is exposed in the opening;removing the first semiconductor layers from the source/drain region ofthe fin structure is exposed in the opening; forming a thirdsemiconductor layer to fully wrap around each of the first semiconductorlayers within the opening; performing a heating process to make an uppersurface of the third semiconductor layer substantially flat; and forminga conductive contact layer over the third semiconductor layer.
 20. Themethod of claim 19, wherein the source/drain regions are (i) portions ofmultiple fins protruding from an isolation insulating layer, or (ii)portions of semiconductor wires horizontally extending over theisolation insulating layer.